A significant trend throughout integrated circuit (IC) development is the downsizing of IC components. As the size reduces, the performance requirements become more stringent. Also, as devices continue to shrink in size, the channel region continues to shrink as well. For metal-oxide-semiconductor field effect transistors (MOSFETs), increased performance requirements have generally been met by aggressively scaling the length of the channel region. The goals of the semiconductor industry is to continue shrinking the size and increasing the speed of individual FETs at the same time. To achieve these goals, fin FETs (FinFETs) or multiple gate transistors are developed, wherein the FinFETs not only improve areal density and current performance but also improve gate control of the channel.
However, one challenge with the decreasing geometry of semiconductor ICs is the formation of unwanted residue in or on the semiconductor substrate. During formation of a shallow trench isolation (STI), it is difficult to define active regions in fine pitch regions because of a narrower line width. In addition, the trenches of the STI may suffer from a serious micro-loading effect between different pitch regions. A method or a profile of removing residue is required.